1. Field of the Invention
This invention relates, in general, to three state gates and more particularly to a non-inverting, glitchless three state gate that does not supply current to an input bus.
2. Background Art
Three state gates have an output which is capable of assuming an active high, an active low, or a high impedance state. Previously known non-inverting, three state gates typically comprise a push-pull output driver stage, a phase splitting stage, and an input stage as illustrated in FIG. 1 which will be discussed in detail hereinafter in the Detailed Description of the Invention. The push-pull output driver stage comprises a dual transistor arrangement wherein an upper transistor is coupled between a DC voltage supply and an output load and a lower transistor is coupled between the output load and ground. In operation a high output voltage is realized at the output terminal by turning on the upper transistor and turning off the lower transistor; a low output voltage is realized by turning off the upper transistor and turning on the lower transistor; and a high impedance is achieved by turning off both transistors.
The phase splitting stage comprises a transistor coupled between the bases of the two transistors of the output stage that would selectively turn on one of the two output stage transistors. The input stage comprises a PNP transistor having a base connected to an input terminal. A first NPN transistor has its base connected to the emitter of the PNP transistor. A second NPN transistor has a base connected to the emitter of the first NPN transistor. The bases of the first NPN transistor, the second NPN transistor, the phase splitting transistor, and the output stage upper transistor are each coupled to an output enable terminal by a diode. A low output enable signal directs current away from the transistor bases through these diodes, thus turning off both of the upper and lower transistors of the output stage, giving a high impedance at the output terminal. A high signal on the output enable terminal reverse biases the diodes, effectively removing their paths from the circuit.
However, when switching from the high impedance state to an active high, this previously known arrangement would have a glitch in the output, wherein the output would tend to go to an active low from the high impedance state prior to going to the active high. This glitch could be avoided by removing the diode coupled between the base of the first NPN transistor (the emitter of the PNP transistor) and the output enable terminal. However, by removing this diode, problems are created in a bus oriented system. Current would then flow to the input bus from the PNP transistor.
Thus, a need exists for an improved non-inverting three state gate having a smooth, glitchless transition from a high impedance state to an active high while preventing current from flowing to the input terminal.